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Data Sheet, Rev. 1.0, May 2008
TLE42754
L o w D r o p o u t Li n e a r F i x e d Vo l t a g e R e g u l a t o r
Automotive Power
Low Dropout Linear Fixed Voltage Regulator
TLE42754
1
Features * * * * * * * * * * * * * *
Overview
Output Voltage 5 V 2% Ouput Current up to 450 mA Very low Current Consumption Power-on and Undervoltage Reset with Programmable Delay Time Reset Low Down to VQ = 1 V Very Low Dropout Voltage Output Current Limitation Reverse Polarity Protection Overtemperature Protection Suitable for Use in Automotive Electronics Wide Temperature Range from -40 C up to 150 C Input Voltage Range from -42 V to 45 V Green Product (RoHS compliant) AEC Qualified
PG-TO252-5
Description The TLE42754 is a monolithic integrated low-dropout voltage regulator in a 5-pin TO-package, especially designed for automotive applications. An input voltage up to 42 V is regulated to an output voltage of 5.0 V. The component is able to drive loads up to 450 mA. It is short-circuit proof by the implemented current limitation and has an integrated overtemperature shutdown. A reset signal is generated for an output voltage VQ,rt of typically 4.65 V. The power-on reset delay time can be programmed by the external delay capacitor. Dimensioning Information on External Components An input capacitor CI is recommended for compensation of line influences. An output capacitor CQ is necessary for the stability of the control loop.
PG-TO263-5
Type TLE42754D TLE42754G Data Sheet
Package PG-TO252-5 PG-TO263-5 2
Marking TLE42754D TLE42754G Rev. 1.0, 2008-05-29
TLE42754
Overview Circuit Description The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any oversaturation of the power element. The component also has a number of internal circuits for protection against: * * * Overload Overtemperature Reverse polarity
Data Sheet
3
Rev. 1.0, 2008-05-29
TLE42754
Block Diagram
2
Block Diagram
I
TLE42754
Q
Protection Circuits
Bandgap Reference GND
Reset Generator
RO
D
Figure 1
Block Diagram
Data Sheet
4
Rev. 1.0, 2008-05-29
TLE42754
Pin Configuration
3
3.1
Pin Configuration
Pin Assignment TLE42754D (PG-TO252-5) and TLE42754G (PG-TO263-5)
P-TO252-5 (D-PAK)
GND
P-TO263-5 (D-PAK)
1 RO DQ
5
AEP02580
GND Q D RO
IEP02528
Figure 2
Pin Configuration (top view)
3.2
Pin Definitions and Functions TLE42754D (PG-TO252-5) and TLE42754G (PGTO263-5)
Symbol I Function Input for compensating line influences, a capacitor to GND close to the IC terminals is recommended Reset Output open collector output; external pull-up resistor to a positive potential required; leave open if the reset function is not needed TLE42754G (PG-TO263-5) only: Ground internally connected to tab Reset Delay Timing connect a ceramic capacitor to GND for adjusting the reset delay time; leave open if the reset function is not needed Output block to GND with a capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in the table "Functional Range" on Page 7 Ground connect to heatsink area
Pin 1
2
RO
3 4
GND D
5
Q
TAB
GND
Data Sheet
5
Rev. 1.0, 2008-05-29
TLE42754
General Product Characteristics
4
4.1
General Product Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings 1) -40 C Tj 150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Input 4.1.1 Output 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 Voltage Voltage Voltage Junction Temperature Storage Temperature ESD Absorption Voltage Parameter Symbol Limit Values Min. Max. 45 7 25 7 150 150 2 500 750 V V V V C C kV V V - - - - - - Human Body Model (HBM)2) Charge Device Model (CDM)3) Charge Device Model (CDM)3) at corner pins Unit Conditions
VI VQ VRO VD Tj Tstg VESD,HBM VESD,CDM
-42 -0.3 -0.3 -0.3 -40 -50 -2 -500 -750
Reset Output Reset Delay Temperature
ESD Absorption
1) Not subject to production test, specified by design. 2) ESD HBM Test according JEDEC JESD22-A114 3) ESD CDM Test according AEC/ESDA ESD-STM5.3.1-1999
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation.
Data Sheet
6
Rev. 1.0, 2008-05-29
TLE42754
General Product Characteristics
4.2
Functional Range
Pos. 4.2.1 4.2.2 4.2.3
Parameter Input Voltage Output Capacitor's Requirements for Stability Junction Temperature
Symbol Min.
Limit Values Max. 42 - 3 150 5.5 22 - -40
Unit V F C
Conditions - -1) -2) -
VI CQ ESR(CQ) Tj
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% 2) relevant ESR value at f = 10 kHz
Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
Data Sheet
7
Rev. 1.0, 2008-05-29
TLE42754
General Product Characteristics
4.3
Pos.
Thermal Resistance
Parameter Symbol Min. Limit Value Typ. 3.7 27 110 57 42 - - - - - Max. K/W K/W K/W K/W K/W -
2)
Unit
Conditions
TLE42754D (PG-TO252-5) 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 TLE42754G (PG-TO263-5) 4.3.9 4.3.10 4.3.11 4.3.12 4.3.13 Junction to Case1) Junction to Ambient
1)
Junction to Case1) Junction to Ambient
1)
RthJC RthJA
- - - - -
footprint only3) 300 mm2 heatsink area on PCB3) 600 mm2 heatsink area on PCB3) -
2)
RthJC RthJA
- - - - -
3.7 27 70 42 33
- - - - -
K/W K/W K/W K/W K/W
footprint only3) 300 mm2 heatsink area on PCB3) 600 mm2 heatsink area on PCB3)
1) not subject to production test, specified by design 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m Cu, 2 x 35m Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 1 copper layer (1 x 70m Cu).
Data Sheet
8
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
5
5.1
Block Description and Electrical Characteristics
Voltage Regulator
The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output capacitor's capacitance and its equivalent series resistor ESR requirements given in the table "Functional Range" on Page 7 have to be maintained. For details see also the typical performance graph "Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ" on Page 12. As the output capacitor also has to buffer load steps it should be sized according to the application's needs. An input capacitor CI is strongly recommended to compensate line influences. Connect the capacitors close to the component's terminals. A protection circuitry prevent the IC as well as the application from destruction in case of catastrophic events. These safeguards contain an output current limitation, a reverse polarity protection as well as a thermal shutdown in case of overtemperature. In order to avoid excessive power dissipation that could never be handled by the pass element and the package, the maximum output current is decreased at input voltages above VI = 28 V. The thermal shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator restarts. This leads to an oscillatory behaviour of the output voltage until the fault is removed. However, junction temperatures above 150 C are outside the maximum ratings and therefore significantly reduce the IC's lifetime. The TLE42754 allows a negative supply voltage. In this fault condition, small currents are flowing into the IC, increasing its junction temperature. This has to be considered for the thermal design, respecting that the thermal protection circuit is not operating during reverse polarity conditions.
Supply
II
I
Q
IQ
Regulated Output Voltage
Saturation Control Current Limitation C CI Temperature Shutdown Bandgap Reference ESR
}
CQ
LOAD
BlockDiagram_VoltageRegulator.vsd
GND
Figure 3
Voltage Regulator
Data Sheet
9
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Electrical Characteristics Voltage Regulator
VI = 13.5 V, -40 C Tj 150 C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified) Pos. 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Parameter Output Voltage Output Voltage Output Voltage Output Current Limitation Load Regulation steady-state Line Regulation steady-state Dropout Voltage1) Symbol Min. Limit Values Typ. 5.0 5.0 5.0 - -15 Max. 5.1 5.1 5.1 1100 - V V V mA mV 1 mA < IQ < 450 mA 9 V < VI < 28 V 1 mA < IQ < 400 mA 6 V < VI < 28 V 1 mA < IQ < 200 mA 6 V < VI < 40 V 4.9 4.9 4.9 450 -30 Unit Conditions
VQ VQ VQ IQ,max VQ,load VQ,line Vdr PSRR
dVQ/dT
VQ = 4.8V IQ = 5 mA to
400 mA
5.1.6 5.1.7 5.1.8 5.1.9 5.1.10 5.1.11
- - - - 151 -
5 250 60 0.5 - 20
15 500 - - 200 -
mV mV dB mV/K C C
Vdr = VI - VQ
Power Supply Ripple Rejection2) Temperature Output Voltage Drift Overtemperature Shutdown Threshold Overtemperature Shutdown Threshold Hysteresis
VI = 8 V VI = 8 V to 32 V IQ = 5 mA IQ = 300 mA fripple = 100 Hz Vripple = 0.5 Vpp
-
Tj,sd Tj,sdh
Tj increasing2) Tj decreasing2)
1) measured when the output voltage VQ has dropped 100mV from the nominal value obtained at VI = 13.5V 2) not subject to production test, specified by design
Data Sheet
10
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics Typical Performance Characteristics Voltage Regulator Output Voltage VQ versus Junction Temperature Tj
5,20
01_VQ_T J.VSD
Output Current IQ versus Input Voltage VI
1000
T j = -40 C
02_IQ_VI.VSD
900
T j = 25 C
5,10
800 700
T j = 150 C
5,00
4,90
V I = 13.5 V I Q = 50 mA
IQ,max [mA]
80 120 160
V Q [V]
600 500 400 300 200 100
4,80
4,70
4,60 -40 0 40
0 0 10 20 30 40 50
T j [C]
Power Supply Ripple Rejection PSRR versus ripple frequency fr)
100 90 80 70
03_PSRR_FR.VSD
V I [V]
Line Regulation VQ,line versus Input Voltage Change VI)
9 8 7 6
04_DVQ_DVI.VSD
T j = -40 C T j = 25 C T j = 150 C
T j = 150 C
PSRR [dB]
V Q [mV]
60 50 40 30 20 10 0 0,01
5 4 3
T j = 25 C
I Q = 10 mA C Q = 22 F
ceramic V I = 13.5 V V ripple = 0.5 Vpp 0,1 1 10 100 1000
T j = -40 C
2 1 0 0 10 20 30 40
f [kHz]
V I [V]
Data Sheet
11
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Load Regulation VQ,load versus Output Current Change IQ
0
05_DVQ_DIQ.VSD
Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ
VI = 8 V
-5
1000
06_ESR_IQ.VSD
100
C Q = 22 F Tj = -40..150 C Unstable Region
V I = 6..28 V
V Q [mV]
-10
Tj = 25 C Tj = 150 C
ESR(C Q) [ ]
Tj = -40 C
10
-15
1
-20
0,1
Stable Region
-25 0 100 200 300 400 500
0,01 0 100 200 300 400 500
I Q [mA]
Dropout Voltage Vdr versus Junction Temperature Tj
500 450 400 350
07_VDR_TJ.VSD
I Q [mA]
I Q = 400 mA
I Q = 300 mA
V DR[mV]
300 250 200 150 100 50 0 -40 0 40 80 120 160
I Q = 100 mA
I Q = 10 mA
T j [C]
Data Sheet
12
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
5.2
Current Consumption
Electrical Characteristics Current Consumption
VI = 13.5 V, -40 C Tj 150 C, positive current flowing into pin
(unless otherwise specified) Pos. 5.2.1 5.2.2 5.2.3 5.2.4 Parameter Current Consumption Iq = II - IQ Symbol Limit Values Min. Typ. Max. - 150 200 - - - 150 5 15 220 10 25 Unit A A mA mA Conditions
Iq
IQ = 1 mA Tj = 25 C IQ = 1 mA Tj = 85 C IQ = 250 mA IQ = 400 mA
Data Sheet
13
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics Typical Performance Characteristics Current Copnsumption Current Consumption Iq versus Output Current IQ (IQ low)
7
V I = 13.5 V
08_IQ_IQ_IQLOW.VSD
Current Consumption Iq versus Output Current IQ
30
V I = 13.5 V
09_IQ_IQ.VSD
6
T j = 150 C
25
T j = 150 C
5
20
I q [mA]
I q [mA]
4
15
T j = 25 C
3
T j = 25 C
10
2
5
1
0 0 50 100 150 200
0 0 100 200 300 400 500
I Q [mA]
Current Consumption Iq versus Input Voltage VI
60
10_IQ_VI.VSD
I Q [mA]
50
40
I q [mA]
30
R LOAD = 12.5
20
10
R LOAD = 500
0 0 10 20 30 40
V I [V]
Data Sheet
14
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
5.3
Reset Function
The reset function provides several features: Output Undervoltage Reset: An output undervoltage condition is indicated by setting the Reset Output RO to "low". This signal might be used to reset a microcontroller during low supply voltage. Power-On Reset Delay Time: The power-on reset delay time trd allows a microcontoller and oscillator to start up. This delay time is the time frame from exceeding the reset switching threshold VRT until the reset is released by switching the reset output "RO" from "low" to "high". The power-on reset delay time trd is defined by an external delay capacitor CD connected to pin D charged by the delay capacitor charge current ID,ch starting from VD = 0 V. If the application needs a power-on reset delay time trd different from the value given in Item 5.3.6, the delay capacitor's value can be derived from the specified values in Item 5.3.6 and the desired power-on delay time:
t rd, new C D = ---------------- x 47nF t rd
with * * *
CD: capacitance of the delay capacitor to be chosen trd,new: desired power-on reset delay time trd: power-on reset delay time specified in this datasheet
For a precise calculation also take the delay capacitor's tolerance into consideration. Reset Reaction Time: The reset reaction time avoids that short undervoltage spikes trigger an unwanted reset "low" signal. The reset reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the external delay capacitor CD (see typical performance graph for details). Hence, the total reset reaction time becomes:
t rr = t rd, int + t rr, d
with * * *
trr: reset reaction time trr,int: internal reset reaction time trr,d: reset discharge
Reset Output Pull-Up Resistor RRO: The Reset Output RO is an open collector output requiring an external pull-up resistor to a voltage VIO, e.g. VQ. In Table "Electrical Characteristics Reset Function" on Page 18 a minimum value for the external resistor RRO is given for the case it is connected to VQ or to a voltage VIO < VQ. If the pull-up resistor shall be connected to a voltage VIO > VQ, use the following formula:
5k R RO = ---------- x V IO VQ
Data Sheet
15
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Supply
I
Q
VDD
Int. Supply Control
CQ ID,ch
RO
RRO
Reset
VRT
VDST
I RO
MicroController
IDR,dsch
GND
BlockDiagram_Reset.vsd
D
GND
CD
Figure 4
Block Diagram Reset Function
Data Sheet
16
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
VI
t VQ VRT t < trr,total
1V
t VD V DU V DRL t VRO t rd trr,total trd t rr,total t rd t rr,total t rd
V RO,low
1V
t
Thermal Shutdown Input Voltage Dip Undervoltage Spike at output Overload
T i mi n g Di a g ra m_ Re se t. vs
Figure 5
Timing Diagram Reset
Data Sheet
17
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Electrical Characteristics Reset Function
VI = 13.5 V, -40 C Tj 150 C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified) Pos. Parameter Symbol Min. Output Undervoltage Reset 5.3.1 Output Undervoltage Reset Switching Thresholds Reset Output Low Voltage Reset Output Sink Current Capability Reset Output Leakage Current Reset Output External Pull-up Resistor to VQ Power On Reset Delay Time Upper Delay Switching Threshold Lower Delay Switching Threshold Delay Capacitor Charge Current Delay Capacitor Reset Discharge Current Delay Capacitor Discharge Time Limit Values Typ. 4.65 Max. 4.8 V Unit Conditions
VRT
4.5
VQ decreasing
Reset Output RO 5.3.2 5.3.3 5.3.4 5.3.5
VRO,low IRO,max IRO,leak RRO
- 0.2 - 5
0.2 - 0 -
0.4 - 10 -
V mA A k
1 V VQ VRT ; IRO = 0.2 mA 1 V VQ VRT ; VRO = 5 V
VRO = 5 V
1 V VQ VRT ; VRO 0.4 V
Reset Delay Timing 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11
trd VDU VDRL ID,ch ID,dch trr,d
10 - - - - -
16 1.8 0.65 5.5 100 0.5
22 - - - - 1
ms V V A mA s
CD = 47 nF
- -
VD = 1 V VD = 1 V
Calculated Value: trr,d = CD*(VDU VDRL)/ ID,dch CD = 47 nF
5.3.12 5.3.13
Internal Reset Reaction Time Reset Reaction Time
trr,int trr,total
- -
4 4.5
7 8
s s
CD = 0 nF1)
Calculated Value:
trr,total = trr,int + trr,d CD = 47 nF
1) parameter not subject to production test; specified by design
Data Sheet
18
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics Typical Performance Characteristics Undervoltage Reset Switching Threshold VRT versus Tj
5
11_VRT_TJ.VSD
Power On Reset Delay Time trd versus Junction Temperature Tj
20 18
12_TRD_TJ.VSD
C D = 47 nF
4,9
16 14 12
4,8
V RT [V]
t rd [ms]
-40 0 40 80 120 160
4,7
10 8
4,6
6 4 2
4,5
4,4
0 -40 0 40 80 120 160
T j [C]
Power On Reset DelayTime trd versus Capacitance CD
90 80 T j = -40 C 70 60 T j = 25 C T j = 150 C
2,5
13_TRD_CD.VSD
T j [C]
Internal Reset Reaction Time trr,int versus Junction Temperature Tj
3,5
14_T RRINT_TJ.VSD
3
50 40 30
t rr,int [s]
0 50 100 150 200 250
t rd [ms]
2
1,5
1
20 10 0
0,5
0 -40 0 40 80 120 160
C D [nF]
T j [C]
Data Sheet
19
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Delay Capacitor Discharge Time trr,d versus Junction Temperature Tj
0,6 C D = 47 nF 0,5
15_TRRD_TJ.VSD
0,4
t rr,d [s]
0,3
0,2
0,1
0 -40 0 40 80 120 160
T j [C]
Data Sheet
20
Rev. 1.0, 2008-05-29
TLE42754
Package Outlines
6
Package Outlines
6.5 +0.15 -0.05 5.7 MAX.
1)
A B
2.3 +0.05 -0.10 0.5 +0.08 -0.04
(4.24) 1 0.1
(5)
9.98 0.5 6.22 -0.2
0.8 0.15
0.9 +0.20 -0.01 0...0.15
0.15 MAX. per side
0.51 MIN.
5 x 0.6 0.1 1.14
0.5 +0.08 -0.04 0.1 B
4.56
0.25
M
AB
1) Includes mold flashes on each side. All metal surfaces tin plated, except area of cut.
Figure 6
PG-TO252-5
Data Sheet
21
Rev. 1.0, 2008-05-29
TLE42754
Package Outlines
4.4 10 0.2 0...0.3 8.5 1) A 1.27 0.1 B 0.05
10.3
(15)
9.25 0.2
7.55 1)
2.4 0.1
0...0.15 5 x 0.8 0.1 4 x 1.7 0.25
M
4.7 0.5
2.7 0.3
0.5 0.1
AB
8 MAX.
0.1 B
1) Typical Metal surface min. X = 7.25, Y = 6.9 All metal surfaces tin plated, except area of cut.
Figure 7 PG-TO263-5
GPT09113
Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Data Sheet 22
Dimensions in mm Rev. 1.0, 2008-05-29
TLE42754
Revision History
7
Version 1.0
Revision History
Date 2008-05-29 Changes final data sheet
Data Sheet
23
Rev. 1.0, 2008-05-29
Edition 2008-05-29 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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